US 12,142,641 B2
Method for making gate-all-around (GAA) device including a superlattice
Keith Doran Weeks, Chandler, AZ (US); Nyles Wynn Cody, Tempe, AZ (US); Marek Hytha, Brookline, MA (US); Robert J. Mears, Wellesley, MA (US); Robert John Stephenson, Duxford (GB); and Hideki Takeuchi, San Jose, CA (US)
Assigned to ATOMERA INCORPORATED, Los Gatos, CA (US)
Filed by Atomera Incorporated, Los Gatos, CA (US)
Filed on Dec. 21, 2022, as Appl. No. 18/069,287.
Application 18/069,287 is a continuation of application No. 17/305,098, filed on Jun. 30, 2021, granted, now 11,837,634.
Claims priority of provisional application 63/047,356, filed on Jul. 2, 2020.
Prior Publication US 2023/0122723 A1, Apr. 20, 2023
Int. Cl. H01L 29/15 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/152 (2013.01) [H01L 29/66477 (2013.01); H01L 29/7849 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A method for making a semiconductor gate-all-around (GAA) device comprising:
forming source and drain regions on a semiconductor substrate;
forming a plurality of semiconductor nanostructures extending between the source and drain regions;
forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement; and
forming at least one superlattice within at least one of the nanostructures, the at least one superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.