| CPC H01L 29/1083 (2013.01) [H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/092 (2013.01); H01L 27/0924 (2013.01); H01L 29/0673 (2013.01); H01L 29/165 (2013.01); H01L 29/66742 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |

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1. A semiconductor structure, comprising:
a substrate;
a fin protruding from the substrate in a first direction, wherein the fin comprises a well region and an anti-punch through region over the well region;
a barrier layer formed over the anti-punch through region;
channel layers formed over the fin and spaced apart from the barrier layer in the first direction;
a first liner layer formed around the fin;
an isolation structure formed over the first liner layer; and
a gate wrapping around the channel layers and extending in a second direction;
wherein a top surface of the barrier layer is higher than a top surface of the first liner layer in a cross-sectional view along the second direction.
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