US 12,142,634 B2
Silicon and silicon germanium nanowire structures
Kelin J. Kuhn, Aloha, OR (US); Seiyon Kim, Portland, OR (US); Rafael Rios, Portland, OR (US); Stephen M. Cea, Hillsboro, OR (US); Martin D. Giles, Portland, OR (US); Annalisa Cappellani, Portland, OR (US); Titash Rakshit, Hillsboro, OR (US); Peter Chang, Portland, OR (US); and Willy Rachmady, Beaverton, OR (US)
Assigned to Sony Group Corporation, Tokyo (JP)
Filed by Sony Group Corporation, Tokyo (JP)
Filed on Apr. 8, 2021, as Appl. No. 17/225,452.
Application 17/225,452 is a continuation of application No. 16/831,692, filed on Mar. 26, 2020, granted, now 10,991,799.
Application 16/831,692 is a continuation of application No. 15/410,649, filed on Jan. 19, 2017, granted, now 10,636,871, issued on Apr. 28, 2020.
Application 15/410,649 is a continuation of application No. 14/789,856, filed on Jul. 1, 2015, granted, now 9,595,581, issued on Mar. 14, 2017.
Application 14/789,856 is a continuation of application No. 14/274,592, filed on May 9, 2014, granted, now 9,129,829, issued on Sep. 8, 2015.
Application 14/274,592 is a continuation of application No. 12/958,179, filed on Dec. 1, 2010, granted, now 8,753,942, issued on Jun. 17, 2014.
Prior Publication US 2021/0226006 A1, Jul. 22, 2021
Int. Cl. H01L 29/06 (2006.01); B82Y 10/00 (2011.01); H01L 21/762 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 29/10 (2006.01); H01L 29/16 (2006.01); H01L 29/165 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0673 (2013.01) [B82Y 10/00 (2013.01); H01L 21/76224 (2013.01); H01L 27/0922 (2013.01); H01L 27/1203 (2013.01); H01L 29/0676 (2013.01); H01L 29/1033 (2013.01); H01L 29/16 (2013.01); H01L 29/165 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/7848 (2013.01); H01L 29/785 (2013.01); H01L 29/78618 (2013.01); H01L 29/78654 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A method of forming a device, the method comprising:
forming an epitaxial silicon germanium over a substrate;
forming an epitaxial silicon over the epitaxial silicon germanium;
patterning the epitaxial silicon disposed over the epitaxial silicon germanium to form fin structures;
forming a sacrificial gate electrode over the fin structures;
forming spacers adjacent to sidewalls of the sacrificial gate electrode and over the fin structures;
removing a semiconductor portion of the fin structures from source/drain regions over the substrate,
forming source/drain structures on the source/drain regions, wherein the source/drain structures define voids between adjacent facet surfaces of the source/drain structures and over the substrate, wherein the adjacent facet surfaces existing on a side of the source/drain structures are oblique to the substrate, and
wherein, in a cross-sectional view, the portions of the source/drain structures opposite the substrate have surfaces without an acute angle;
removing the sacrificial gate electrode from between the spacers; and
removing one of the epitaxial silicon or the epitaxial silicon germanium from the fin structures disposed between the spacers.