US 12,142,620 B2
Complementary metal-oxide semiconductor (CMOS) image sensors with saddle-gate source follower for imaging pixels
Yunfei Gao, San Diego, CA (US); Tae Seok Oh, San Diego, CA (US); and Jinwen Xiao, San Diego, CA (US)
Assigned to SHENZHEN GOODIX TECHNOLOGY CO., LTD., Shenzhen (CN)
Filed by Shenzhen Goodix Technology Co., Ltd., Shenzhen (CN)
Filed on Nov. 15, 2021, as Appl. No. 17/527,065.
Claims priority of provisional application 63/127,494, filed on Dec. 18, 2020.
Prior Publication US 2022/0199663 A1, Jun. 23, 2022
Int. Cl. H01L 27/14 (2006.01); H01L 27/146 (2006.01)
CPC H01L 27/14612 (2013.01) [H01L 27/14643 (2013.01); H01L 27/14689 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A complementary metal-oxide semiconductor (CMOS) imaging sensor (CIS) comprising:
an imaging pixel comprising:
a semiconductor substrate;
a photo-sensor block comprising at least one photo-sensor configured to accumulate photocharge responsive to exposure to illumination and to transfer the accumulated photocharge to a floating diffusion region for readout;
a first oxide diffusion region;
a second oxide diffusion region separate from the first oxide diffusion region; and
in-pixel circuitry coupled with the floating diffusion region to convert the accumulated photocharge to a pixel output signal, the in-pixel circuitry comprising:
a reset block disposed on the first oxide diffusion region and coupled with the floating diffusion region;
a select block disposed on the second oxide diffusion region; and
a saddle-gate source-follower transistor block disposed on the second oxide diffusion region and comprising:
a channel region having a three-dimensional geometry that includes an upper portion having an axial length dimension and a planar width dimension, a first axial side portion defined by a first side trench to have the axial length dimension and a first fender depth dimension, and a second axial side portion defined by a second side trench to have the axial length dimension and a second fender depth dimension, the channel region being implanted with channel doping;
a gate oxide layer formed over at least the upper portion, the first axial side portion, and the second axial side portion of the channel region; and
a saddle-gate structure formed on the gate oxide layer to have a seat portion extending over the upper portion of the channel region, a first fender portion extending over the first axial side portion of the channel region, and a second fender portion extending over the second axial side portion of the channel region,
such that the first and second fender portions are buried below an upper surface of the semiconductor substrate.