US 12,142,607 B2
Semiconductor device
Cheol Kim, Suwon-si (KR); Dongkwon Kim, Suwon-si (KR); and Hyunho Jung, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 5, 2022, as Appl. No. 17/713,834.
Claims priority of application No. 10-2021-0080703 (KR), filed on Jun. 22, 2021.
Prior Publication US 2022/0406775 A1, Dec. 22, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/092 (2013.01) [H01L 21/0259 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 29/0665 (2013.01); H01L 29/41733 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate;
a first active region and a second active region extending parallel to each other in a first direction, on the substrate;
an isolation layer disposed between the first active region and the second active region;
a line structure disposed on the substrate, overlapping the first and second active regions and the isolation layer, and extending in a second direction that is perpendicular to the first direction;
a first source/drain region disposed on the first active region;
a second source/drain region disposed on the second active region;
a common contact plug disposed on a first side of the line structure, contacting the first source/drain region and the second source/drain region, and overlapping the isolation layer; and
an interlayer insulating layer disposed on a second side of the line structure, on the isolation layer,
wherein the line structure is disposed on the isolation layer and between the common contact plug and the interlayer insulating layer,
the line structure comprises a first gate structure overlapping the first active region and extending on the isolation layer, a second gate structure overlapping the second active region and extending on the isolation layer, and an insulating separation pattern disposed between the first gate structure and the second gate structure and extending into the isolation layer,
at least a portion of the insulating separation pattern is disposed between the common contact plug and the interlayer insulating layer,
the insulating separation pattern has a first side surface and a second side surface opposing each other in the first direction, and a third side surface and a fourth side surface opposing each other in the second direction,
at least one of the first side surface and the second side surface of the insulating separation pattern comprises a first portion, a second portion on a level lower than the first portion, and a third portion on a level lower than the second portion, and
a slope of each of the first portion and the third portion is steeper than a slope of the second portion.