US 12,142,579 B2
Package structure and manufacturing method thereof
Tsung-Fu Tsai, Changhua County (TW); Shih-Ting Lin, Taipei (TW); Szu-Wei Lu, Hsinchu (TW); Chen-Hsuan Tsai, Taitung (TW); and I-Ting Huang, Kaohsiung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 18, 2023, as Appl. No. 18/354,633.
Application 18/354,633 is a continuation of application No. 17/739,186, filed on May 9, 2022.
Application 17/739,186 is a continuation of application No. 16/944,102, filed on Jul. 30, 2020, granted, now 11,355,454, issued on Jun. 7, 2022.
Prior Publication US 2023/0361052 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/6835 (2013.01); H01L 23/5383 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/35121 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a redistribution circuit structure comprising dielectric layers;
a wiring substrate disposed on the redistribution circuit structure;
an insulating encapsulation laterally encapsulating the wiring substrate; and
a reinforcement structure comprising reinforcement pattern layers and reinforcement vias, the reinforcement pattern layers and the dielectric layers are stacked alternately, the reinforcement vias penetrate through the dielectric layers to connect the reinforcement pattern layers, at least one of the reinforcement pattern layers is embedded in the insulating encapsulation, and the reinforcement structure is electrically floating.