US 12,142,574 B2
Semiconductor devices and methods of manufacture
Yao-Te Huang, Hsinchu (TW); Hong-Wei Chan, Hsinchu (TW); Yung-Shih Cheng, Hsinchu (TW); Jiing-Feng Yang, Zhubei (TW); and Hui Lee, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 30, 2021, as Appl. No. 17/390,104.
Claims priority of provisional application 63/166,525, filed on Mar. 26, 2021.
Prior Publication US 2022/0310527 A1, Sep. 29, 2022
Int. Cl. H01L 23/544 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01)
CPC H01L 23/544 (2013.01) [H01L 21/76877 (2013.01); H01L 23/5226 (2013.01); H01L 2223/54426 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
forming a metallization layer in a dielectric layer overlying an interconnect structure, the interconnect structure being over a device wafer with a first integrated circuit; and
forming a dummy insertion structure within the dielectric layer, the dummy insertion structure having a stepped pattern density and including a first pattern density region of a first set of dummy insertion features and a second pattern density region of a second set of dummy insertion features, the second pattern density region is embedded within a perimeter of the first pattern density region, wherein a first density of patterns in the first pattern density region is different from a second density of patterns in the second pattern density region, and the first pattern density region and the second pattern density region are both within a same level of the dielectric layer.