| CPC H01L 23/5386 (2013.01) [H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 25/0657 (2013.01)] | 20 Claims |
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1. A semiconductor package, comprising:
a substrate;
a first semiconductor chip positioned over the substrate and electrically connected to the substrate;
a plurality of second semiconductor chips positioned over the first semiconductor chip in a vertical direction, wherein the plurality of second semiconductor chips include a lowermost second semiconductor chip and an uppermost second semiconductor chip;
a third semiconductor chip positioned over the upper most second semiconductor chip stack;
a plurality of first bonding structures with a first pitch between the substrate and the first semiconductor chip, wherein each of the plurality of first bonding structures has a first height;
a plurality of second boding structures with a second pitch between the second semiconductor chips, wherein each of the plurality of second bonding structures has a second height; and
a plurality of third bonding structures with a third pitch between the uppermost second semiconductor chip and the third semiconductor chip, wherein each of the plurality of third bonding structures has a third height,
wherein the third height is greater than the second height.
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