US 12,142,570 B2
Composite bridge die-to-die interconnects for integrated-circuit packages
Bok Eng Cheah, Bukit Gambir (MY); Jackson Chung Peng Kong, Tanjung Tokong (MY); Jenny Shio Yin Ong, Bayan Lepas (MY); Ping Ping Ooi, Butterworth (MY); and Seok Ling Lim, Kulim (MY)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 27, 2022, as Appl. No. 17/975,223.
Application 17/975,223 is a continuation of application No. 17/025,990, filed on Sep. 18, 2020, granted, now 11,521,932.
Claims priority of application No. PI2019007401 (MY), filed on Dec. 11, 2019.
Prior Publication US 2023/0048835 A1, Feb. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5384 (2013.01) [H01L 21/565 (2013.01); H01L 23/3185 (2013.01); H01L 24/11 (2013.01); H01L 24/16 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first die and a second die;
an interconnect bridge coupled between the first die and the second die;
a passive device located laterally between the first die and the second die, the passive device coupled to the interconnect bridge; and
an insulator material that contacts the first die and the second die, sidewalls of the passive device, and the interconnect bridge.