US 12,142,569 B2
Integrated chip for standard logic performance improvement having a back-side through-substrate-via and method for forming the integrated chip
Min-Feng Kao, Chiayi (TW); Dun-Nian Yaung, Taipei (TW); Jen-Cheng Liu, Hsin-Chu (TW); and Hsun-Ying Huang, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 22, 2021, as Appl. No. 17/382,570.
Application 17/382,570 is a continuation of application No. 16/710,271, filed on Dec. 11, 2019, granted, now 11,107,767.
Application 16/710,271 is a continuation of application No. 16/176,547, filed on Oct. 31, 2018, granted, now 10,566,288, issued on Feb. 18, 2020.
Application 16/176,547 is a continuation of application No. 15/143,950, filed on May 2, 2016, granted, now 10,147,682, issued on Dec. 4, 2018.
Claims priority of provisional application 62/260,808, filed on Nov. 30, 2015.
Prior Publication US 2021/0351134 A1, Nov. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/525 (2006.01)
CPC H01L 23/5384 (2013.01) [H01L 21/6835 (2013.01); H01L 21/76804 (2013.01); H01L 21/76832 (2013.01); H01L 21/76883 (2013.01); H01L 21/76898 (2013.01); H01L 23/3171 (2013.01); H01L 23/481 (2013.01); H01L 23/522 (2013.01); H01L 23/5283 (2013.01); H01L 24/00 (2013.01); H01L 24/02 (2013.01); H01L 23/3114 (2013.01); H01L 23/3192 (2013.01); H01L 23/525 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/6834 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/03002 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05073 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/11002 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13183 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/01013 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
a first plurality of interconnects within a first inter-level dielectric (ILD) structure disposed along a first side of a first substrate, the first ILD structure surrounding a first transistor device;
a conductive pad arranged along a second side of the first substrate;
a first through-substrate-via (TSV) physically contacting an interconnect of the first plurality of interconnects and a first surface of the conductive pad;
a second plurality of interconnects within a second ILD structure disposed on a second substrate, the second ILD structure surrounding a second transistor device;
a second TSV extending from a first interconnect of the first plurality of interconnects to through the second substrate and to a second interconnect of the second plurality of interconnects;
a conductive bump arranged on a second surface of the conductive pad opposing the first surface; and
wherein the second TSV has a greater width than the first TSV.