US 12,142,567 B2
Coreless architecture and processing strategy for EMIB-based substrates with high accuracy and high density
Xiao Di Sun Zhou, Tempe, AZ (US); Debendra Mallik, Chandler, AZ (US); and Xiaoying Guo, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 17, 2019, as Appl. No. 16/387,167.
Prior Publication US 2020/0335443 A1, Oct. 22, 2020
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01)
CPC H01L 23/5381 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/6835 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/16 (2013.01); H01L 24/95 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/95001 (2013.01); H01L 2924/3511 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a plurality of conductive layers over a package substrate, wherein the plurality of conductive layers include a first conductive layer and first-level interconnects (FLIs) in the package substrate;
a solder resist surrounding the FLIs, wherein the solder resist has a top surface that is substantially coplanar to a plurality of top surfaces of the FLIs;
a bridge having a top with conductive pads, the conductive pads coupled directly to the first conductive layer with a plurality of solder balls, the bridge in a cavity in the package substrate, and the bridge having sidewalls, wherein the first conductive layer is coupled to the FLIs;
an encapsulation layer laterally surrounding the bridge in the cavity, the encapsulation layer on the top of the bridge and in contact with the conductive pads of the bridge, the encapsulation layer along less than an entirety of the sidewalls of the bridge, and the encapsulation layer having a bottommost surface above a bottommost surface of the bridge; and
a dielectric over the plurality of conductive layers, the bridge, and the solder resist of the package substrate.