US 12,142,561 B2
Integrated device and integrated passive device comprising magnetic material
Kai Liu, Phoenix, AZ (US); Je-Hsiung Lan, San Diego, CA (US); and Jonghae Kim, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 25, 2022, as Appl. No. 17/705,041.
Prior Publication US 2023/0307355 A1, Sep. 28, 2023
Int. Cl. H01L 23/522 (2006.01); H01L 49/02 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/5227 (2013.01) [H01L 23/5222 (2013.01); H01L 23/5226 (2013.01); H01L 28/10 (2013.01); H01L 24/13 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An integrated device comprising:
a die substrate comprising a plurality of transistors;
an interconnection portion coupled to the die substrate, the interconnection portion comprising:
at least one die dielectric layer;
a plurality of die interconnects coupled to the plurality of transistors; and
a passivation layer coupled to the at least one die dielectric layer; and
a packaging portion coupled to the interconnection portion, the packaging portion comprising:
at least one magnetic layer; and
a plurality of metallization interconnects coupled to the plurality of die interconnects,
wherein the passivation layer is located (i) between the die substrate and the plurality of metallization interconnects and (ii) between the die substrate and the at least one magnetic layer.