US 12,142,557 B2
Integrated chip having a back-side power rail
Shin-Yi Yang, New Taipei (TW); Ming-Han Lee, Taipei (TW); and Shau-Lin Shue, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jun. 27, 2023, as Appl. No. 18/341,831.
Application 18/341,831 is a division of application No. 17/394,622, filed on Aug. 5, 2021, granted, now 11,735,513.
Prior Publication US 2023/0343695 A1, Oct. 26, 2023
Int. Cl. H01L 23/50 (2006.01); H01L 21/8234 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01)
CPC H01L 23/50 (2013.01) [H01L 21/823475 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/088 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated chip comprising:
a semiconductor device comprising a first source/drain structure, a second source/drain structure, a stack of channel structures, and a gate structure, wherein the stack of channel structures and the gate structure are between and border the first and second source/drain structures, and wherein the gate structure extends in a closed path to surround the stack of channel structures;
a first conductive wire overlying and spaced from the semiconductor device, wherein the first conductive wire comprises a first stack of conductive layers; and
a first conductive contact extending through a dielectric layer from the first conductive wire to the first source/drain structure,
wherein a bottom surface of the first source/drain structure, opposite a top surface of the first source/drain structure, and a bottom surface of the gate structure face away from the first conductive wire, wherein the bottom surface of the gate structure is below the bottom surface of the first source/drain structure, and wherein the first conductive contact is on the top surface of the first source/drain structure.