US 12,142,538 B2
Fabrication method of semiconductor device and test method of semiconductor device
Atsushi Shoji, Matsumoto (JP); and Soichi Yoshida, Matsumoto (JP)
Assigned to FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed by FUJI ELECTRIC CO., LTD., Kanagawa (JP)
Filed on Jan. 23, 2022, as Appl. No. 17/581,966.
Claims priority of application No. 2021-044127 (JP), filed on Mar. 17, 2021.
Prior Publication US 2022/0301948 A1, Sep. 22, 2022
Int. Cl. H01L 21/66 (2006.01); H01L 21/225 (2006.01); H01L 29/40 (2006.01)
CPC H01L 22/14 (2013.01) [H01L 21/225 (2013.01); H01L 29/401 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A fabrication method of a semiconductor device comprising:
forming a semiconductor element including a gate insulating film in a semiconductor substrate and forming a metal electrode above the semiconductor substrate;
plating the metal electrode;
annealing the semiconductor substrate;
applying a voltage corresponding to a thickness of the gate insulating film to the gate insulating film after the annealing; and
measuring a threshold voltage of the semiconductor element after the voltage applying, and judging a quality of the semiconductor element based on a measurement result.