US 12,142,528 B2
3D chip with shared clock distribution network
Javier A. DeLaCruz, San Jose, CA (US); Steven L. Teig, Menlo Park, CA (US); Ilyas Mohammed, San Jose, CA (US); and Eric M. Nequist, Saratoga, CA (US)
Assigned to Adeia Semiconductor Inc., San Jose, CA (US)
Filed by Adeia Semiconductor Inc., San Jose, CA (US)
Filed on Dec. 27, 2022, as Appl. No. 18/146,709.
Application 18/146,709 is a continuation of application No. 16/953,113, filed on Nov. 19, 2020, granted, now 11,557,516.
Application 16/953,113 is a continuation of application No. 16/889,698, filed on Jun. 1, 2020, granted, now 10,886,177, issued on Jan. 5, 2021.
Application 16/889,698 is a continuation of application No. 15/976,817, filed on May 10, 2018, granted, now 10,672,663, issued on Jun. 2, 2020.
Application 15/976,817 is a continuation in part of application No. 15/725,030, filed on Oct. 4, 2017, granted, now 10,522,352, issued on Dec. 31, 2019.
Claims priority of provisional application 62/619,910, filed on Jan. 21, 2018.
Claims priority of provisional application 62/575,184, filed on Oct. 20, 2017.
Claims priority of provisional application 62/575,240, filed on Oct. 20, 2017.
Claims priority of provisional application 62/575,259, filed on Oct. 20, 2017.
Claims priority of provisional application 62/405,833, filed on Oct. 7, 2016.
Prior Publication US 2023/0137580 A1, May 4, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/822 (2006.01); H01L 23/00 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01); H01L 27/06 (2006.01); H01L 21/768 (2006.01); H01L 23/50 (2006.01)
CPC H01L 21/8221 (2013.01) [H01L 23/5286 (2013.01); H01L 24/10 (2013.01); H01L 24/26 (2013.01); H01L 24/49 (2013.01); H01L 25/0657 (2013.01); H01L 27/0688 (2013.01); H01L 21/76898 (2013.01); H01L 23/50 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01)] 26 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) device comprising a first IC die and a second IC die direct-bonded to and facing each other, wherein the IC device is configured to distribute a clock signal to one or both of the first and second IC dies through clock distribution interconnect structures formed adjacent to a bonding interface between the first and second IC dies.