US 12,142,527 B2
Method and system for regulating plasma dicing rates
Antonius Hendrikus Jozef Kamphuis, Nijmegen (NL); Ernst Eiper, Graz (AT); Johannes Cobussen, Beuningen (NL); and Chantal Claude Dijkstra, Veenendaal (NL)
Assigned to NXP B.V., Austin, TX (US)
Filed by NXP B.V., Eindhoven (NL)
Filed on Jun. 14, 2023, as Appl. No. 18/334,421.
Application 18/334,421 is a division of application No. 16/721,083, filed on Dec. 19, 2019, granted, now 11,721,586.
Prior Publication US 2023/0326796 A1, Oct. 12, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/82 (2006.01); G01R 31/28 (2006.01); H01L 21/66 (2006.01)
CPC H01L 21/82 (2013.01) [G01R 31/2831 (2013.01); G01R 31/2856 (2013.01); H01L 22/32 (2013.01); H01L 22/34 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of regulating plasma etch rate in an intersection region between two dicing lanes, the method comprising:
forming integrated circuitry within one or more metal layers on a wafer, wherein
the integrated circuitry is arranged in a grid pattern of a plurality of device die regions including a first semiconductor device die region, a second semiconductor device die region, a third semiconductor device die region, and a fourth semiconductor device die region, and
the first semiconductor device die region neighbors the second semiconductor device die region and is separated from the second semiconductor device die region by a first dicing lane,
the third semiconductor device die region neighbors the first semiconductor device die region and is separated from the first semiconductor device die region by a second dicing lane, wherein the first and second dicing lanes intersect at the intersection region,
the fourth semiconductor device die region neighbors the second semiconductor device die region and is separated from the second semiconductor device die region by the second dicing lane and the fourth semiconductor device die region neighbors the third semiconductor device die region and is separated from the third semiconductor device die region by the first dicing lane; and
forming a first conductor having a continuous shape and coupled to circuitry of the first semiconductor device die, the first conductor comprising:
a first portion of the first conductor extending from the circuitry of the first semiconductor device die at a first side of the first semiconductor device die into the first dicing lane and extending toward the second semiconductor device die, entering the second semiconductor device die at a first side, and extending into a seal ring region of the second semiconductor device die,
a second portion of the first conductor extending from the seal ring region of the second semiconductor device die at a second side of the second semiconductor device die different from the first side of the second semiconductor device into the second dicing lane and extending toward the fourth semiconductor device die, entering the fourth semiconductor device die at a first side, and extending into a seal ring region of the fourth semiconductor device die,
a third portion of the first conductor extending from the seal ring region of the fourth semiconductor device die at a second side of the fourth semiconductor device die different from the first side of the fourth semiconductor device into the first dicing lane and extending toward the third semiconductor device die, entering the third semiconductor device die at a first side, and extending into a seal ring region of the third semiconductor device die, and
a fourth portion of the first conductor extending from the seal ring region of the third semiconductor device die at a second side of the third semiconductor device die different from the first side of the third semiconductor device into the second dicing lane and extending toward the first semiconductor device die, entering the first semiconductor device die, and extending into a seal ring region of the first semiconductor device die,
wherein the first, second, third, and fourth portions of the first conductor together form the continuous shape of the first conductor.