US 12,142,509 B2
Electrostatic chuck with seal surface
Patrick G. Breiling, Portland, OR (US); Michael Philip Roberts, Tigard, OR (US); Chloe Baldasseroni, Tigard, OR (US); Ishtak Karim, Portland, OR (US); Adrien LaVoie, Newberg, OR (US); and Ramesh Chandrasekharan, Portland, OR (US)
Assigned to Lam Research Corporation, Fremont, CA (US)
Appl. No. 15/733,687
Filed by Lam Research Corporation, Fremont, CA (US)
PCT Filed Apr. 4, 2019, PCT No. PCT/US2019/025866
§ 371(c)(1), (2) Date Sep. 29, 2020,
PCT Pub. No. WO2019/195601, PCT Pub. Date Oct. 10, 2019.
Claims priority of provisional application 62/652,546, filed on Apr. 4, 2018.
Prior Publication US 2021/0013080 A1, Jan. 14, 2021
Int. Cl. H01L 21/683 (2006.01); C23C 16/458 (2006.01); H01J 37/32 (2006.01); H01L 21/687 (2006.01)
CPC H01L 21/6833 (2013.01) [C23C 16/4581 (2013.01); H01J 37/32082 (2013.01); H01J 37/32091 (2013.01); H01J 37/32715 (2013.01); H01L 21/6831 (2013.01); H01L 21/68735 (2013.01); H01L 21/6875 (2013.01); H01J 2237/2005 (2013.01)] 33 Claims
OG exemplary drawing
 
1. A semiconductor processing system comprising:
a processing chamber;
at least one processing station in the processing chamber;
an electrostatic chuck in the at least one processing station, the electrostatic chuck having a body that includes:
an upper annular seal surface that is planar, is perpendicular to a vertical center axis of the body, and has a radial thickness,
a lower recess surface that is offset from the upper annular seal surface by a first distance,
a plurality of micro-contact areas (MCAs) protruding from the lower recess surface, each MCA having a top surface that is offset from the lower recess surface by a second distance less than or equal to the first distance, and
one or more electrodes within the body, wherein:
the upper annular seal surface is configured to support an outer edge of a semiconductor substrate when the semiconductor substrate is being supported by the electrostatic chuck,
the upper annular seal surface and the top surfaces of the MCAs are configured to support the semiconductor substrate when the semiconductor substrate is being supported by the electrostatic chuck, and
the one or more electrodes are configured to provide, when powered by a power supply, at least one electrostatic clamping force on the semiconductor substrate as part of supporting the semiconductor substrate on the electrostatic chuck;
the power supply electrically connected to the one or more electrodes, wherein the power supply comprises a direct current (DC) power supply and a radio frequency (RF) power supply;
an end effector configured to position the semiconductor substrate on the electrostatic chuck; and
a controller having a memory and one or more processors, the memory storing computer-executable instructions, which, when executed by the one or more processors, cause the one or more processors to:
cause, at least in part, the end effector to position the semiconductor substrate on the electrostatic chuck;
cause, while positioning the semiconductor substrate on the electrostatic chuck, the power supply to provide DC power to the one or more electrodes to provide the electrostatic clamping force on the semiconductor substrate;
cause, after positioning the semiconductor substrate on the electrostatic chuck, the power supply to stop providing DC power and thereby stop providing the electrostatic clamping force on the semiconductor substrate; and
cause, after positioning the semiconductor substrate on the electrostatic chuck and stopping providing DC power to the one or more electrodes, the power supply to provide RF power, and not DC power, to the one or more electrodes to generate a plasma in the at least one processing station during at least one processing operation, wherein the electrostatic clamping force is not applied to the semiconductor substrate while generating the plasma during the at least one processing operation.