US 12,142,489 B2
Semiconductor device manufacturing method and plasma processing method
Mamoru Yakushiji, Tokyo (JP); Kenichi Kuwahara, Tokyo (JP); and Makoto Miura, Tokyo (JP)
Assigned to HITACHI HIGH-TECH CORPORATION, Tokyo (JP)
Appl. No. 17/642,312
Filed by Hitachi High-Tech Corporation, Tokyo (JP)
PCT Filed Mar. 4, 2021, PCT No. PCT/JP2021/008520
§ 371(c)(1), (2) Date Mar. 11, 2022,
PCT Pub. No. WO2022/185491, PCT Pub. Date Sep. 9, 2022.
Prior Publication US 2023/0411167 A1, Dec. 21, 2023
Int. Cl. H01L 21/3213 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/775 (2006.01); H01L 29/786 (2006.01)
CPC H01L 21/32136 (2013.01) [H01L 21/823412 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 27/088 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device manufacturing method for manufacturing a semiconductor device including Gate All Around type Field effect transistors, the method comprising:
a step of removing an organic film on an n-type channel;
a step of removing a work function control metal film on a bottom surface between channels;
a step of forming a protective film onto an organic film on a p-type channel in a fluorinated state; and
a step of removing a work function control metal film on the n-type channel.
 
9. A plasma processing method for forming Gate All Around type Field effect transistors, the method comprising:
a step of removing an organic film on an n-type channel;
a step of removing a work function control metal film on a bottom surface between channels;
a step of forming a protective film onto an organic film on a p-type channel; and
a step of removing a work function control metal film on the n-type channel,
wherein the step of forming the protective film includes a first step of exposing plasma generated with a fluorine-containing gas to the n-type channel and the p-type channel.