| CPC H01L 21/32105 (2013.01) [H10B 43/27 (2023.02)] | 13 Claims | 

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               1. A method of manufacturing a semiconductor memory device comprising: 
            forming a plurality of first layers and a plurality of second layers alternately stacked in a first direction; 
                forming a hole penetrating the plurality of first layers and the plurality of second layers; 
                forming a charge accumulation layer and a semiconductor layer in the hole; 
                forming a trench penetrating the plurality of first layers and the plurality of second layers; 
                removing the plurality of first layers to form a plurality of removed areas at positions corresponding to the plurality of first layers; 
                forming a conductive material in the plurality of removed areas and in the trench; 
                recessing a part of the conductive material to form a conductive layer facing the semiconductor layer via the charge accumulation layer and having a rounded portion at an end on a side of the trench; and 
                forming an insulating material in the trench. 
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