US 12,142,485 B2
Semiconductor structure and manufacturing method thereof
Hung-Pin Chang, New Taipei (TW); Tsang-Jiuh Wu, Hsinchu (TW); and Wen-Chih Chiou, Miaoli County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 13, 2023, as Appl. No. 18/167,888.
Application 18/167,888 is a continuation of application No. 17/460,337, filed on Aug. 30, 2021, granted, now 11,594,420.
Prior Publication US 2023/0197464 A1, Jun. 22, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/31 (2006.01); H01L 21/027 (2006.01); H01L 21/3065 (2006.01); H01L 21/3105 (2006.01); H01L 21/463 (2006.01); H01L 21/02 (2006.01)
CPC H01L 21/31055 (2013.01) [H01L 21/0273 (2013.01); H01L 21/3065 (2013.01); H01L 21/463 (2013.01); H01L 21/02063 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A manufacturing method of a through substrate via, comprising:
forming a protective liner within an opening of a dielectric layer, wherein the opening exposes a portion of a semiconductor substrate underlying the dielectric layer;
removing the portion of the semiconductor substrate through the opening, wherein an overhang portion is formed at a top edge of the semiconductor substrate and masked by the protective liner after the removing;
removing the overhang portion of the semiconductor substrate, the protective liner, and a portion of the dielectric layer adjoining the protective liner to form a via hole; and
forming a conductive material in the via hole.