US 12,142,481 B2
Forming passivation stack having etch stop layer
Roger Carroll, Rosemount, MN (US)
Assigned to Polar Semiconductor, LLC, Bloomington, MN (US)
Filed by Polar Semiconductor, LLC, Bloomington, MN (US)
Filed on Jan. 5, 2022, as Appl. No. 17/647,086.
Prior Publication US 2023/0215727 A1, Jul. 6, 2023
Int. Cl. H01L 21/02 (2006.01); H01L 21/463 (2006.01); H01L 21/465 (2006.01); H01L 21/469 (2006.01)
CPC H01L 21/02422 (2013.01) [H01L 21/463 (2013.01); H01L 21/465 (2013.01); H01L 21/469 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A method comprising:
forming a metallization layer on a portion of an integrated circuit comprising transistors, logic circuits or capacitors, wherein the metallization layer has a gap separating portions of the metallization layer;
depositing a first glass layer on the metallization layer;
depositing an etch stop layer on the first glass layer, wherein the etch stop layer has a recess between the separated portions of the metallization layer;
depositing a second glass layer on the etch stop layer; and
polishing the second glass layer down to at least a surface of the etch stop layer and leaving a separate portion of the second glass layer in the recess between the separated portions of the metallization layer.