US 12,142,440 B2
Multilayer ceramic capacitor
Hideaki Tanaka, Nagaokakyo (JP); Daiki Fukunaga, Nagaokakyo (JP); and Koji Moriyama, Nagaokakyo (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Nagaokakyo (JP)
Filed on Sep. 20, 2023, as Appl. No. 18/370,652.
Application 18/370,652 is a continuation of application No. 17/203,846, filed on Mar. 17, 2021, granted, now 11,798,746.
Application 17/203,846 is a continuation of application No. 16/793,041, filed on Feb. 18, 2020, granted, now 11,120,945, issued on Sep. 14, 2021.
Application 16/793,041 is a continuation of application No. 16/568,573, filed on Sep. 12, 2019, granted, now 10,720,281, issued on Jul. 21, 2020.
Application 16/568,573 is a continuation of application No. 16/285,286, filed on Feb. 26, 2019, granted, now 10,600,575, issued on Mar. 24, 2020.
Application 16/285,286 is a continuation of application No. 16/208,924, filed on Dec. 4, 2018, granted, now 10,410,791, issued on Sep. 10, 2019.
Application 16/208,924 is a continuation of application No. 15/960,694, filed on Apr. 24, 2018, granted, now 10,325,726, issued on Jun. 18, 2019.
Application 15/960,694 is a continuation of application No. 15/210,933, filed on Jul. 15, 2016, granted, now 9,984,824, issued on May 29, 2018.
Claims priority of application No. 2015-142975 (JP), filed on Jul. 17, 2015.
Prior Publication US 2024/0013982 A1, Jan. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01G 4/005 (2006.01); H01G 4/12 (2006.01); H01G 4/232 (2006.01); H01G 4/30 (2006.01)
CPC H01G 4/30 (2013.01) [H01G 4/005 (2013.01); H01G 4/232 (2013.01); H01G 4/1218 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A multilayer ceramic capacitor comprising:
a laminated body including a plurality of dielectric layers and a plurality of internal electrodes laminated in a laminating direction; and
a plurality of external electrodes connected to respective ones of the internal electrodes; wherein
the laminated body includes:
an inner layer portion including the plurality of dielectric layers and the plurality of internal electrodes;
outer layer portions sandwiching the inner layer portion in the laminating direction; and
side margin portions sandwiching the inner layer portion and the outer layer portions in a width direction perpendicular or substantially perpendicular to the laminating direction; and
the side margin portions include a plurality of side margin layers in which an amount of Si included in a first side margin layer closest to the plurality of internal electrodes is lower than an amount of Si included in at least one other side margin layer.