US 12,142,348 B2
Memory device comprising programmable command-and-address and/or data interfaces
Ian Shaeffer, Los Gatos, CA (US); Lawrence Lai, San Jose, CA (US); Fan Ho, San Ramon, CA (US); David A. Secker, San Jose, CA (US); Wayne S. Richardson, Saratoga, CA (US); Akash Bansal, Santa Clara, CA (US); Brian S. Leibowitz, San Francisco, CA (US); and Kyung Suk Oh, Cupertino, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on Sep. 1, 2023, as Appl. No. 18/460,413.
Application 18/460,413 is a continuation of application No. 17/531,151, filed on Nov. 19, 2021, granted, now 11,783,879.
Application 17/531,151 is a continuation of application No. 16/987,157, filed on Aug. 6, 2020, granted, now 11,211,105, issued on Dec. 28, 2021.
Application 16/987,157 is a continuation of application No. 16/222,909, filed on Dec. 17, 2018, granted, now 10,770,124, issued on Sep. 8, 2020.
Application 16/222,909 is a continuation of application No. 15/623,261, filed on Jun. 14, 2017, granted, now 10,192,598, issued on Jan. 29, 2019.
Application 15/623,261 is a continuation of application No. 14/813,028, filed on Jul. 29, 2015, granted, now 9,734,879, issued on Aug. 15, 2017.
Application 14/813,028 is a continuation of application No. 13/753,360, filed on Jan. 29, 2013, granted, now 9,117,496, issued on Aug. 25, 2015.
Claims priority of provisional application 61/592,521, filed on Jan. 30, 2012.
Prior Publication US 2024/0096387 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 8/12 (2006.01); G11C 5/02 (2006.01); G11C 5/04 (2006.01); G11C 5/06 (2006.01); G11C 7/10 (2006.01); G11C 8/18 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01)
CPC G11C 8/12 (2013.01) [G11C 5/02 (2013.01); G11C 5/04 (2013.01); G11C 5/06 (2013.01); G11C 5/063 (2013.01); G11C 7/1012 (2013.01); G11C 7/1045 (2013.01); G11C 8/18 (2013.01); H01L 24/49 (2013.01); H01L 25/0657 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45099 (2013.01); H01L 2224/48095 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48471 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/49433 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2924/00012 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dynamic random access memory device, comprising:
a first set of pins located on a first side of a line of symmetry, the first set of pins to receive a first memory access command;
a second set of pins located on a second side of the line of symmetry and in a mirror configuration with respect to the first set of pins, the second set of pins to receive a second memory access command;
a set of data interfaces to transfer data corresponding to the first memory access command and the second memory access command; and
a third set of pins to configure a width of the set of data interfaces, the width to be based on voltage levels detected on the third set of pins.