US 12,142,344 B2
Techniques for reducing DRAM power usage in performing read and write operations
Gautam Bhatia, Mountain View, CA (US)
Assigned to NVIDIA CORPORATION, Santa Clara, CA (US)
Filed by NVIDIA CORPORATION, Santa Clara, CA (US)
Filed on Oct. 4, 2022, as Appl. No. 17/959,586.
Claims priority of provisional application 63/257,522, filed on Oct. 19, 2021.
Prior Publication US 2023/0124767 A1, Apr. 20, 2023
Int. Cl. G11C 7/10 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/1096 (2013.01) [G11C 7/1069 (2013.01); G11C 7/222 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer-implemented method for performing a memory access operation on a memory device, the method comprising:
prior to receiving the memory access operation, receiving an indicator that identifies the memory access operation as including at least one of a read operation or a write operation;
enabling a first circuit based on the indicator; and
maintaining a disabled state of a second circuit based on the indicator.