US 12,142,340 B2
Testing system and testing method
Shih-Chieh Lin, Hsinchu (TW); Sheng-Lin Lin, Hsinchu (TW); and Li-Wei Deng, Hsinchu (TW)
Assigned to Realtek Semiconductor Corporation, Hsinchu (TW)
Filed by Realtek Semiconductor Corporation, Hsinchu (TW)
Filed on Jul. 22, 2022, as Appl. No. 17/814,232.
Claims priority of application No. 111101719 (TW), filed on Jan. 14, 2022.
Prior Publication US 2023/0230652 A1, Jul. 20, 2023
Int. Cl. G11C 29/56 (2006.01); G11C 29/18 (2006.01)
CPC G11C 29/56004 (2013.01) [G11C 29/18 (2013.01); G11C 29/56012 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A testing system, comprising:
a plurality of memory circuits; and
a testing circuit coupled to the memory circuits, wherein the testing circuit is configured to perform a read/write operation on the memory circuits, and each of the memory circuits has a read/write starting time point corresponding to the read/write operation,
wherein the testing circuit is further configured to control the read/write starting time points of the memory circuits to be different from each other,
wherein the memory circuits have different total work time intervals,
wherein the memory circuits comprise a first memory circuit and a second memory circuit, wherein a storage capacity of the first memory circuit is greater than a storage capacity of the second memory circuit, wherein the read/write starting time point of the first memory circuit is earlier than the read/write starting time point of the second memory circuit,
wherein each of the first memory circuit and the second memory circuit has a read/write ending time point corresponding to the read/write operation, and the read/write ending time point of the second memory circuit is aligned with or earlier than the read/write ending time point of the first memory circuit.