CPC G11C 29/52 (2013.01) [G11C 7/1096 (2013.01); G11C 7/20 (2013.01)] | 20 Claims |
1. A memory controller including:
a normal data path that directs storage operations during a normal memory read/write operation after a power startup of a memory chip; and
a priming path that includes a priming module, wherein the priming module directs memory priming operations during the power startup of the memory chip, including forwarding a priming pattern for loading in a write pattern mode register in the memory chip and selection of a memory address in the memory chip for initialization with the priming pattern.
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