US 12,142,337 B2
System and method for parallel memory test
Nitesh Mishra, Kanpur (IN); and Nikita Naresh, Bangalore (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Aug. 22, 2023, as Appl. No. 18/453,400.
Application 18/453,400 is a continuation of application No. 17/538,982, filed on Nov. 30, 2021, granted, now 11,776,656.
Claims priority of application No. 202141018707 (IN), filed on Apr. 23, 2021.
Prior Publication US 2023/0402124 A1, Dec. 14, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/46 (2006.01); G11C 29/12 (2006.01); G11C 29/18 (2006.01); G11C 29/38 (2006.01); H03K 19/173 (2006.01)
CPC G11C 29/46 (2013.01) [G11C 29/12015 (2013.01); G11C 29/18 (2013.01); G11C 29/38 (2013.01); H03K 19/1737 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A device, comprising:
a controller coupled to memory components via a forward data path, the controller configured to provide memory address signals and a controller clock signal to the memory components via the forward data path, the forward data path including first circuitry configured to provide test-enable signals to the memory components that enable the memory components to read, according to the memory address signals and based on the controller clock signal, stored memory values; and
a signature register coupled to the memory components via a backward data path, the backward data path including second circuitry configured to receive from the memory components a set of memory signals, and combine the set of memory signals into a combined signal, each memory signal of the set of memory signals associated with a respective one of the memory components and including at least one stored memory value read from the corresponding memory component, the signature register configured to calculate a test signature based on the combined signal, and compare the test signature to an expected signature.