US 12,142,336 B2
Intelligent memory device test rack
Gary D. Hamor, Mead, OR (US); Michael R. Spica, Eagle, ID (US); Donald Shepard, Longmont, CO (US); Patrick Caraher, Longmont, CO (US); and João Elmiro da Rocha Chaves, Middleton, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on Apr. 8, 2022, as Appl. No. 17/716,972.
Application 17/716,972 is a continuation of application No. 16/719,707, filed on Dec. 18, 2019, granted, now 11,328,789.
Prior Publication US 2022/0230700 A1, Jul. 21, 2022
Int. Cl. G11C 29/44 (2006.01); G06F 9/50 (2006.01); G11C 29/22 (2006.01); G11C 29/36 (2006.01); G11C 29/56 (2006.01)
CPC G11C 29/44 (2013.01) [G06F 9/5016 (2013.01); G11C 29/22 (2013.01); G11C 29/36 (2013.01); G11C 29/56 (2013.01); G11C 2029/5602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
detecting, by a processing device allocated to a memory device test board of a distributed test platform, that a memory sub-system has engaged with a memory device test resource of the memory device test board, the memory device test resource separately allocated for the memory sub-system engaged with the memory device test resource and comprising a plurality of test condition components that are designated for the memory device test resource, wherein the plurality of test condition components comprise a temperature controller that is configured to apply a test temperature condition and a voltage controller that is configured to apply a test voltage condition to the memory sub-system engaged with the memory device test resource in isolation from other memory device test resources of the memory device test board;
identifying, by the processing device, a test to be performed for a memory device of the memory sub-system, wherein the test comprises first instructions to be executed by a memory sub-system controller of the memory sub-system in performance of the test and second instructions to be executed by the processing device in performance of the test, wherein the second instructions are to cause the plurality of test condition components of the memory device test resource to generate at least the test temperature condition and the test voltage condition to be applied to the memory device while the memory sub-system controller executes the first instructions;
responsive to transmitting the first instructions to the memory sub-system controller, executing the second instructions; and
receiving, from one or more test resource monitoring components of the memory device test resource, additional data associated with the test performed for the memory device, wherein the additional data indicates two or more of a temperature of the test resource during the performance of the test, a voltage of a power supply signal provided to the memory device during the performance of the test, a current of the power supply signal provided to the memory device during the performance of the test, or a humidity of an environment of the memory device test resource during the performance of the test.