US 12,142,331 B2
Memory controller and operating method thereof
Seung Yeol Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 30, 2022, as Appl. No. 18/060,437.
Claims priority of application No. 10-2022-0065011 (KR), filed on May 26, 2022.
Prior Publication US 2023/0386594 A1, Nov. 30, 2023
Int. Cl. G11C 29/10 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/10 (2013.01) [G11C 29/12005 (2013.01); G11C 29/12015 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory controller, comprising:
a test controller configured to perform a test on a memory device using a target pattern selected from among a plurality of test patterns for each of a plurality of test modes, in which test signals have voltage and time conditions that are set differently;
a test information storage configured to store test result information including values associated with fail bits of the memory device measured in the test; and
a machine learning processor configured to detect a defect acceleration mode, from among the plurality of test modes, in which a defect of the memory device is accelerated using the test result information obtained in the test performed using the target pattern.