US 12,142,328 B2
Erasing and erasing verification for three-dimensional NAND memory
Kaijin Huang, Hubei (CN)
Assigned to Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed by Yangtze Memory Technologies Co., Ltd., Hubei (CN)
Filed on Sep. 22, 2022, as Appl. No. 17/950,810.
Prior Publication US 2024/0112742 A1, Apr. 4, 2024
Int. Cl. G11C 16/16 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 16/08 (2013.01); G11C 16/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of erase and erase verification for a memory device, comprising:
applying a first erase voltage to erase memory cells of the memory device, wherein the first erase voltage is incrementally increased by a first erase step voltage until the memory cells pass an initial erase verification using an initial erase verification voltage that is higher than an erase verification voltage by the first erase step voltage;
after the memory cells pass the initial erase verification, determining whether the memory cells pass or fail sub-erase verifications by applying sub-erase verification voltages, wherein the sub-erase verification voltages are in a range between the erase verification voltage and the initial erase verification voltage; and
applying a second erase voltage to erase the memory cells after the sub-erase verifications, wherein the second erase voltage is increased from the first erase voltage by a second erase step voltage that is smaller than the first erase step voltage and is determined according to whether the memory cells pass or fail the sub-erase verifications.