US 12,142,326 B2
Adaptive programming delay scheme in a memory sub-system
Yu-Chung Lien, San Jose, CA (US); and Zhenming Zhou, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by MICRON TECHNOLOGY, INC., Boise, ID (US)
Filed on May 24, 2022, as Appl. No. 17/752,590.
Prior Publication US 2023/0386583 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/32 (2013.01) [G11C 16/10 (2013.01); G11C 16/349 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device operatively coupled with the memory device, the processing device configured to:
receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device;
determine a value of a metric reflecting a state of the set of memory cells;
determine, using a look-up table, a delay and a size of a subset of the set of memory cells, the delay and the size corresponding to the value of the metric reflecting the state, wherein the look-up table correlates metric values with respective delay values and with respective sizes of the subset of memory cells; and
perform a programming operation with respect to the subset of the set of memory cells, wherein the programming operation comprises the delay between a first pass of the programming operation and a second pass of the programming operation.