CPC G11C 16/26 (2013.01) [G11C 8/12 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/3459 (2013.01); G11C 2213/00 (2013.01)] | 19 Claims |
1. A semiconductor storage device comprising:
a memory cell array including a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively, wherein the plurality of bit lines are grouped into a plurality of bit line groups; and
a control circuit configured to:
receive a read command and first address information specifying one or more of the bit line groups;
in response to the read command, read data selectively from each memory string that is connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data; and
write data of a first bit size according to a mode of writing data of a second bit size that is greater than the first bit size.
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