US 12,142,323 B2
Foggy-fine drain-side select gate re-program for on-pitch semi-circle drain side select gates
Xiaoyu Che, San Jose, CA (US); and Yanjie Wang, San Jose, CA (US)
Assigned to SanDisk Technologies LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Sep. 1, 2022, as Appl. No. 17/901,197.
Prior Publication US 2024/0079061 A1, Mar. 7, 2024
Int. Cl. G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/16 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage, the plurality of memory holes arranged in rows comprising each of a plurality of strings; and
a control means coupled to the drain-side select gate transistors of the plurality of memory holes and configured to:
program the transistor threshold voltage of the drain-side select gate transistors of the plurality of memory holes associated with at least one of the strings to an initial transistor threshold voltage using a plurality of pulses increasing in magnitude by a first transistor step amount during each of a plurality of foggy loops of a foggy program operation, and
program the transistor threshold voltage of the drain-side select gate transistors of the plurality of memory holes associated with at least one of the strings to a target transistor threshold voltage using a plurality of pulses increasing in magnitude by a second transistor step amount during each of a plurality of fine loops of a fine program operation, the first transistor step amount being greater than the second transistor step amount.