| CPC G11C 16/08 (2013.01) | 7 Claims |
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1. A semiconductor storage device comprising:
a block including a plurality of memory cells;
a word line connected to gates of the plurality of memory cells;
a plurality of bit lines connected respectively to one ends of the plurality of memory cells;
a first wiring;
a connection transistor configured to electrically connect the first wiring to the word line based on a signal supplied to a gate of the connection transistor;
a block decoder configured to supply the signal to the gate of the connection transistor; and
a voltage generation circuit including
a first node from which a first voltage for generating the signal is supplied to the block decoder,
a second node from which a second voltage is supplied to the first wiring, and
a voltage difference generation circuit connected between the first node and the second node, wherein
the voltage difference generation circuit includes
a first transistor having
a first terminal connected to the first node,
a gate connected to the first node, and
a second terminal,
a second transistor having
a first terminal connected to the second terminal of the first transistor,
a gate connected to the second terminal of the first transistor, and
a second terminal connected to the second node, and
at least one third transistor each having
a first terminal connected to the first node,
a gate connected to the gate of the second transistor, and
a second terminal connected to the second node, and
the at least one third transistor, all together, has a current drivability greater than a current drivability of the second transistor.
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