| CPC G11C 16/0433 (2013.01) [G11C 16/26 (2013.01); G11C 16/32 (2013.01)] | 18 Claims |
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1. A memory device, comprising:
a plurality of memory cell strings, each including a plurality of memory cells coupled between a drain select line and a source select line;
a peripheral circuit configured to, using a plurality of read voltages, perform a read operation that reads data that is stored in a selected memory cell that is included in a selected memory cell string, among the plurality of memory cell strings; and
an operation controller configured to control the peripheral circuit to perform:
the read operation by using a first read voltage, among the plurality of read voltages;
a first potential adjustment operation after performing the read operation; and
the read operation, after performing the first potential adjustment operation, by using a second read voltage that is lower than the first read voltage,
wherein the first potential adjustment operation is an operation that applies a first turn-on voltage to unselected source select lines that are coupled to unselected memory cell strings, among the plurality of memory cell strings, for a first period and thereafter applies a ground voltage to the unselected source select lines.
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