| CPC G11C 13/004 (2013.01) [G06F 7/5443 (2013.01)] | 9 Claims |
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1. A memory device, comprising:
a plurality of computing memory cells, each of the computing memory cells stores a weight value, receives an input value and generates an output value, each of the computing memory cells comprising:
a transistor, connected to a bit line and a word line, the transistor receives a sensing current through the bit line and receives an input voltage through the word line, when the sensing current flows through the transistor the computing memory cell generates a first voltage difference between a drain and a source of the transistor in response to the input voltage through the word line, and the first voltage difference is an output voltage of the computing memory cell;
wherein, the input voltage corresponds to the input value, the first voltage difference corresponds to the output value, and the output value is equal to a product of the input value and the weight value.
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