US 12,142,315 B2
Low power multi-level cell (MLC) programming in non-volatile memory structures
Xiang Yang, Santa Clara, CA (US); Muhammad Masuduzzaman, Chandler, AZ (US); and Jiacen Guo, Cupertino, CA (US)
Assigned to SanDisk Technologies LLC
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on May 26, 2022, as Appl. No. 17/825,193.
Prior Publication US 2023/0386569 A1, Nov. 30, 2023
Int. Cl. G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01)
CPC G11C 11/5628 (2013.01) [G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for programming a memory array of a non-volatile memory structure, comprising:
initiating a programming operation with respect to a population of MLC type memory cells comprising the memory array, the population of MLC type memory cells being in electrical communication with a plurality of bit lines, wherein the programming operation comprises:
in a first program pulse, programming a first programmable state according to a first programming voltage;
in a second program pulse, programming a second programmable state according to a second programming voltage; and
in a third program pulse, programming a third programmable state according to a third programming voltage, wherein
during each of the first program pulse, second program pulse, and third program pulse, applying:
an inhibit condition to a first set of bit lines of the plurality of bit lines of the memory array; and
a zero voltage condition to a second set of bit lines of the plurality of bit lines of the memory array, the second set of bit lines being different than the first set of bit lines, such that less than half of adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.