| CPC G11C 11/2273 (2013.01) [G11C 11/221 (2013.01)] | 20 Claims |
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1. A memory device, comprising:
a plate line;
a pair of ferroelectric layers implementing a pair of memory cells and coupled to opposite sides of the plate line;
a pair of digit lines each coupled to a respective ferroelectric layer of the pair of ferroelectric layers; and
a sense amplifier coupled to the pair of digit lines and configured to sense and amplify voltages received at the pair of digit lines from the respective memory cells, wherein the sense amplifier comprises a threshold voltage compensated latch that comprises:
a plurality of p-channel transistors configured to compensate for process, voltage, or temperature variation mismatches between the threshold voltages of the plurality of p-channel transistors;
a switch network comprising:
a first pair of switches configured to selectively connect drain terminals of the plurality of p-channel transistors to respective gate terminals of the plurality of p-channel transistors in a threshold voltage compensation configuration; and
a current switch that couples source terminals of the plurality of p-channel transistors to a current source during threshold voltage compensation using the threshold voltage compensation configuration, wherein the switch network is configured to disconnect each of the plurality of p-channel transistors from the current source and the pair of digit lines during at least one phase of the threshold voltage compensation.
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