	US 12,142,310 B2
	Method of fabricating pedestal based memory devices using pocket integration
Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Niloy Mukherjee, San Ramon, CA (US); Amrita Mathuriya, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing, Inc., San Francisco, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/485,161.
Application 17/485,161 is a continuation of application No. 17/465,796, filed on Sep. 2, 2021, granted, now 11,942,133.
Prior Publication US 2023/0070073 A1, Mar. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/522 (2006.01); G11C 11/22 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/535 (2006.01); H01L 23/538 (2006.01); H01L 49/02 (2006.01); H03K 19/185 (2006.01); H10B 53/20 (2023.01); H10B 53/30 (2023.01)

CPC G11C 11/221 (2013.01) [H01L 21/76802 (2013.01); H01L 21/76805 (2013.01); H01L 21/76831 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/53209 (2013.01); H01L 23/53228 (2013.01); H01L 23/53242 (2013.01); H01L 23/53257 (2013.01); H01L 23/535 (2013.01); H01L 23/5381 (2013.01); H01L 23/5386 (2013.01); H01L 28/55 (2013.01); H01L 28/60 (2013.01); H01L 28/65 (2013.01); H03K 19/185 (2013.01); H10B 53/20 (2023.02); H10B 53/30 (2023.02)]

17 Claims

1. A method of fabricating a device structure, the method comprising:

forming a first conductive interconnect in a dielectric in a memory region and a second conductive interconnect in a logic region;

depositing an etch stop layer on the dielectric and on the first conductive interconnect and on the second conductive interconnect;

etching and removing the etch stop layer from the memory region but not from the logic region;

depositing an electrode material on the first conductive interconnect and on the etch stop layer, wherein depositing the electrode material includes depositing the electrode material on a sidewall of the etch stop layer at an interface between the memory region and the logic region;

depositing a material layer stack including ferroelectric material or paraelectric material on the electrode material;

forming a memory device by etching the material layer stack, wherein the etching forms the memory device directly above the first conductive interconnect and a spacer of the material layer stack adjacent to the electrode material on the sidewall of the etch stop layer;

depositing an encapsulation layer on the memory device on the electrode material, and on the spacer of the material layer stack;

forming a mask on the encapsulation layer, wherein forming the mask further comprises forming the mask above the memory device and forming on the encapsulation layer deposited on the spacer of the material layer stack;

etching the encapsulation layer and exposing the electrode material;

etching the electrode material, wherein etching the electrode material comprises:

forming an electrode structure under the memory device;

leaving a first portion of the electrode material adjacent to the sidewall of the etch stop layer; and

leaving a second portion of the encapsulation layer on the spacer of the material layer stack and on surfaces of the electrode material;

blanket depositing a dielectric layer;

forming a first opening in the dielectric layer, the first opening exposing the second conductive interconnect in the logic region;

forming an interconnect via in the first opening and a metal line on the interconnect via by depositing a conductive material in the first opening;

forming a second opening in the dielectric layer and in the encapsulation layer in the memory region, the second opening exposing the memory device; and

forming a via electrode in the second opening by depositing the conductive material in the second opening.