US 12,142,309 B2
Low resistance MTJ antifuse circuitry designs and methods of operation
Syed M. Alam, Austin, TX (US)
Assigned to Everspin Technologies, Inc., Chandler, AZ (US)
Filed by Everspin Technologies, Inc., Chandler, AZ (US)
Filed on Jun. 23, 2022, as Appl. No. 17/847,265.
Claims priority of provisional application 63/313,419, filed on Feb. 24, 2022.
Prior Publication US 2023/0267982 A1, Aug. 24, 2023
Int. Cl. G11C 11/00 (2006.01); G11C 11/16 (2006.01); H01L 23/525 (2006.01); H10N 50/10 (2023.01); H10N 50/80 (2023.01)
CPC G11C 11/1695 (2013.01) [G11C 11/1657 (2013.01); G11C 11/1673 (2013.01); G11C 11/1675 (2013.01); H01L 23/5252 (2013.01); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An antifuse circuit, comprising:
a plurality of magnetoresistive tunnel junction (MTJ) antifuse bitcells including a first MTJ antifuse bitcell and a second MTJ antifuse bitcell, wherein each MTJ antifuse bitcell of the plurality of MTJ antifuse bitcells includes:
an MTJ having a first electrode and a second electrode and a magnetoresistive stack/structure disposed therebetween, wherein the MTJ is configured in only one of: (i) a programmed antifuse state or (ii) unprogrammed antifuse state, wherein if the MTJ is configured in the unprogrammed antifuse state, the MTJ is configurable in an unprogrammed low state and an unprogrammed high state, and
a first select transistor electrically coupled to the first electrode of the MTJ of the associated MTJ antifuse bitcell, wherein the first select transistor includes a gate;
a first reference resistor;
a second select transistor, electrically coupled to the first reference resistor, wherein the second select transistor includes a gate;
a plurality of electrical conductors, including first and second electrical conductors, wherein the first MTJ antifuse bitcell is coupled to the first electrical conductor and the first reference resistor is coupled to the second electrical conductor;
a sense amplifier having a first input electrically coupled to the first electrical conductor and a second input electrically coupled to the second electrical conductor; and
wherein, in a first operation, (i) the first select transistor of the first MTJ antifuse bitcell is responsively enabled, via a voltage applied to the gate thereof, to electrically connect the MTJ of the first MTJ antifuse bitcell to the sense amplifier via the first electrical conductor and (ii) the second select transistor is responsively enabled, via a voltage applied to the gate thereof, to electrically connect the reference resistor to the sense amplifier via the second electrical conductor, and wherein the sense amplifier is configured to sense whether the MTJ of the first MTJ antifuse bitcell is in the programmed antifuse state or the unprogrammed antifuse state.