US 12,142,238 B2
Display device
Hiroyuki Miyake, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Apr. 20, 2023, as Appl. No. 18/137,259.
Application 18/137,259 is a continuation of application No. 17/134,724, filed on Dec. 28, 2020, granted, now 11,636,819, issued on Apr. 25, 2023.
Application 17/134,724 is a continuation of application No. 16/190,205, filed on Nov. 14, 2018, granted, now 10,885,861, issued on Jan. 5, 2021.
Application 16/190,205 is a continuation of application No. 15/852,669, filed on Dec. 22, 2017, granted, now 10,147,378, issued on Dec. 4, 2018.
Application 15/852,669 is a continuation of application No. 15/433,629, filed on Feb. 15, 2017, granted, now 9,852,708, issued on Dec. 26, 2017.
Application 15/433,629 is a continuation of application No. 14/474,330, filed on Sep. 2, 2014, granted, now 9,583,063, issued on Feb. 28, 2017.
Claims priority of application No. 2013-189539 (JP), filed on Sep. 12, 2013.
Prior Publication US 2023/0252952 A1, Aug. 10, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/36 (2006.01); G11C 19/28 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01)
CPC G09G 3/3677 (2013.01) [G11C 19/28 (2013.01); G11C 19/287 (2013.01); G02F 1/134336 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G09G 2300/0814 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/06 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0223 (2013.01); G09G 2330/021 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A display device comprising:
a plurality of scan lines comprising at least a first scan line and a second scan line positioned next to the first scan line;
a first pulse output circuit electrically connected to one end of the first scan line;
a second pulse output circuit electrically connected to one end of the second scan line;
a first transistor;
a second transistor; and
a pixel portion positioned between the first pulse output circuit and the second pulse output circuit in a planar view,
wherein one of a source and a drain of the first transistor is directly connected to the other end of the first scan line,
wherein one of a source and a drain of the second transistor is directly connected to the other end of the second scan line,
wherein the other of the source and the drain of the first transistor is directly connected to a first power supply potential line,
wherein the other of the source and the drain of the second transistor is directly connected to a second power supply potential line,
wherein the other of the source and the drain of the second transistor is directly connected to a second power supply potential line,
wherein a gate of the first transistor is electrically connected to a first signal line different from the plurality of scan lines,
wherein a gate of the second transistor is electrically connected to a second signal line different from the plurality of scan lines,
wherein the other and of the first scan line is not directly connected to any transistor other than the first transistor outside the pixel portion, and
wherein the other end of the second scan line is not directly connected to any transistor other than the second transistor outside the pixel portion.