| CPC G09G 3/3266 (2013.01) [G09G 3/32 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G11C 19/28 (2013.01)] | 20 Claims |
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1. A shift register, comprising:
an input circuit coupled to an input signal terminal, a first clock signal terminal and a first node; and the input circuit being configured to transmit an input signal provided by the input signal terminal to the first node under control of a first clock signal provided by the first clock signal terminal;
a first output circuit coupled to the first node, a first output signal terminal and a scan signal terminal; and the first output circuit being configured to transmit a first output signal provided by the first output signal terminal to the scan signal terminal under control of a potential at the first node;
a first control circuit at least coupled to the input signal terminal, a first voltage signal terminal, the first clock signal terminal, a second voltage signal terminal, a second clock signal terminal, a third output signal terminal and a second node; and the first control circuit being configured to transmit a third output signal provided by the third output signal terminal to the second node at least under control of the input signal provided by the input signal terminal, a second clock signal provided by the second clock signal terminal, and the first clock signal provided by the first clock signal terminal;
a second control circuit coupled to the first node and the second node; and the second control circuit being configured to control the potential at the first node and a potential at the second node to be two inverted potentials; and
a second output circuit coupled to the second node, a second output signal terminal and the scan signal terminal; and the second output circuit being configured to transmit a second output signal provided by the second output signal terminal to the scan signal terminal under control of the potential at the second node.
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