| CPC G09G 3/3233 (2013.01) [G09G 2300/0842 (2013.01); G09G 2310/0286 (2013.01); G09G 2330/021 (2013.01); H10K 59/35 (2023.02)] | 15 Claims |
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1. A semiconductor device comprising a first circuit and a second circuit,
wherein the first circuit comprises a first wiring, a second wiring, a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
wherein a gate of the first transistor is electrically connected to the second circuit through the first wiring,
wherein a gate of the second transistor, one of a source and a drain of the third transistor, and one of a source and a drain of the fourth transistor are electrically connected to the second circuit through the second wiring,
wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the fifth transistor,
wherein a first clock signal is input to the other of the source and the drain of the first transistor,
wherein a first potential is supplied to the other of the source and the drain of the second transistor,
wherein a second clock signal is input to a gate of the third transistor and a gate of the fifth transistor,
wherein a second potential is supplied to the other of the source and the drain of the third transistor,
wherein a third clock signal is input to a gate of the fourth transistor,
wherein a third potential is supplied to the other of the source and the drain of the fourth transistor,
wherein a difference between the third potential and the first potential is larger than a difference between the second potential and the first potential,
wherein the second circuit is configured to supply a first control potential to the first wiring based on a first signal and a second signal input to the second circuit, and
wherein the second circuit is configured to supply a second control potential to the second wiring based on the first signal and the second signal.
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