US 12,142,208 B2
Pixel drive circuit, driving method thereof and display panel
Zhu Wang, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/438,448
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Chengdu (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Nov. 30, 2020, PCT No. PCT/CN2020/132866
§ 371(c)(1), (2) Date Sep. 12, 2021,
PCT Pub. No. WO2022/110179, PCT Pub. Date Jun. 2, 2022.
Prior Publication US 2023/0110045 A1, Apr. 13, 2023
Int. Cl. G09G 3/3233 (2016.01); G09G 3/3275 (2016.01)
CPC G09G 3/3233 (2013.01) [G09G 3/3275 (2013.01); G09G 2300/0426 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/061 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A pixel drive circuit, comprising:
a drive transistor having a first electrode connected to a first node, a second electrode connected to a second node, and a gate connected to a third node;
a data writing circuit connected to the first node and a data signal terminal for transmitting a signal of the data signal terminal to the first node in response to a control signal;
a compensation circuit connecting the second node and the third node for connecting the second node and the third node in response to a control signal;
a light-emitting control circuit connected to the first electrode and the second electrode of the drive transistor, a first power supply terminal, a first electrode of a light-emitting unit, and an enable signal terminal, for connecting the first power supply terminal and an electrode of the drive transistor and connecting the first electrode of the light-emitting unit and another electrode of the drive transistor in response to a signal of the enable signal terminal; and
a storage circuit connected between the first power supply terminal and the third node; and
a reset circuit comprising:
a first transistor having a first electrode connected to the third node, a second electrode connected to the first electrode of the light-emitting unit, and a gate connected to a reset signal terminal; and
a second transistor having a first electrode connected to the second electrode of the first transistor, a second electrode connected to an initial signal terminal, and a gate connected to the reset signal terminal;
wherein the first transistor and the second transistor are N-type oxide transistors, and the drive transistor is a P-type low-temperature polysilicon transistor, and
wherein the compensation circuit comprises a fourth transistor, the fourth transistor is connected to a gate of the drive transistor via a first connecting portion, and a projection of a channel region of the fourth transistor on a base substrate and a projection of a channel region of the first transistor on the base substrate are located on different sides of a projection of the drive transistor on the base substrate.