US 12,142,205 B2
Power supply, light emitting display device and driving method thereof
Jung Jae Kim, Paju-si (KR); Dong Won Park, Paju-si (KR); and Yong Chul Kwon, Paju-si (KR)
Assigned to LG DISPLAY CO., LTD., Seoul (KR)
Filed by LG Display Co., Ltd., Seoul (KR)
Filed on Oct. 31, 2022, as Appl. No. 17/977,558.
Claims priority of application No. 10-2021-0192845 (KR), filed on Dec. 30, 2021.
Prior Publication US 2023/0215351 A1, Jul. 6, 2023
Int. Cl. G09G 3/3225 (2016.01)
CPC G09G 3/3225 (2013.01) [G09G 2300/0842 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/061 (2013.01); G09G 2320/0233 (2013.01); G09G 2330/00 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A light emitting display device comprising:
a display panel configured to display an image;
a driver configured to drive the display panel; and
a power supply configured to supply a high-level voltage to a first power line of the display panel,
wherein the power supply comprises a voltage controller configured to:
receive, from the driver, a vertical synchronization signal and current amount information of the high-level voltage for driving of the display panel, and
boost the high-level voltage to be supplied to the display panel during a vertical blank period, based on the vertical synchronization signal and the current amount information of the high-level voltage,
wherein the power supply is configured to store a fed-back voltage in a compensation capacitor included in the power supply to use the fed-back voltage as a reference value for boosting of the high-level voltage to be supplied to the display panel, and
wherein the voltage controller comprises:
an error amplifier configured to output a voltage control signal for adjusting the high-level voltage;
an output current sensing circuit configured to supply sensing results of sensed current from the first power line to a first inverting terminal of the error amplifier;
a first control transistor configured to supply a reference voltage to a non-inverting terminal of the error amplifier, in response to the vertical synchronization signal;
a second control transistor configured to supply a compensation voltage stored in the compensation capacitor to a second inverting terminal of the error amplifier, in response to an inverted vertical synchronization signal generated through inversion of the vertical synchronization signal; and
a third control transistor configured to store a high-level voltage fed back from the first power line in the compensation capacitor, in response to an inverted and delayed vertical synchronization signal generated through delay of the inverted vertical synchronization signal.