CPC G09G 3/32 (2013.01) [G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0247 (2013.01); G09G 2320/045 (2013.01); G09G 2330/021 (2013.01)] | 20 Claims |
1. A display panel, comprising:
a first gate driving circuit providing a first gate driving signal;
a second gate driving circuit providing a second gate driving signal;
a third gate driving circuit providing a third gate driving signal;
a fourth gate driving circuit providing a scanning signal; and
a pixel circuit, comprising:
a driving transistor, wherein a gate of the driving transistor is connected to a first node, a first electrode of the driving transistor is connected to a second node, and a second electrode of the driving transistor is connected to a third node;
a writing transistor, wherein the writing transistor is connected in series between a data line and the second node or the third node, and a gate of the writing transistor is connected to the scanning signal;
an initialization module, wherein the initialization module is connected to at least one of the first node, the second node, or the third node, to perform resetting based on at least one of the first gate driving signal or the second gate driving signal; and
a compensation transistor, wherein the compensation transistor is connected in series between the first node and the second node or the third node, and a gate of the compensation transistor is connected to the third gate driving signal,
wherein the compensation transistor remains a turned-on state in only one continuous time period in each frame, and the initialization module and the writing transistor are turned on in a time-sharing manner in the continuous time period.
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