| CPC G09G 3/32 (2013.01) [G09G 3/2096 (2013.01); G09G 2300/026 (2013.01); G09G 2320/0247 (2013.01); G09G 2360/04 (2013.01); G09G 2360/06 (2013.01)] | 10 Claims |

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1. A flicker reduction device of a display apparatus, the flicker reduction device comprising:
a frame memory configured to store image data of an input frame synchronized with an input frame frequency varying over time;
a first circuit configured to output a first control signal when a plurality of fixed active periods based on a reference frame frequency are allocated within each input frame time corresponding to the input frame frequency, and output a second control signal when only one fixed active period is allocated within each input frame time; and
a second circuit configured to copy the image data of the input frame according to the first control signal and output image data of a plurality of input frames according to the reference frame frequency, and configured to output the image data of the input frame according to the reference frame frequency without copying according to the second control signal, and
wherein, when the reference frame frequency is an integer multiple of the input frame frequency, the second circuit performs control so that an output frame time is equal to the input frame time, and
when the reference frame frequency is a non-integer multiple of the input frame frequency, the second circuit performs control so that the output frame time differs from the input frame time.
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