US 12,141,893 B2
Cache architecture for image warp processing systems and methods
Ido Y Soffair, Tel-Aviv (IL); Uri Nix, Haifa (IL); Yung-Chin Chen, Saratoga, CA (US); Jim C Chou, San Jose, CA (US); Jian Zhou, Pleasanton, CA (US); Assaf Menachem, Hod Hasharon (IL); and Sorin C Cismas, Saratoga, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 19, 2022, as Appl. No. 17/933,409.
Prior Publication US 2024/0095871 A1, Mar. 21, 2024
Int. Cl. G06T 1/20 (2006.01); G06T 1/60 (2006.01)
CPC G06T 1/60 (2013.01) [G06T 1/20 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
an electronic display configured to display an image based on warped image data; and
image processing circuitry configured to generate the warped image data by warping input image data to account for one or more distortions associated with displaying the image, wherein the image processing circuitry comprises a two-stage cache architecture comprising a first cache and a second cache, wherein warping the input image data comprises:
generating mapping data indicative of a warp between an input image space of the input image data and an output image space of the warped image data;
fetching the input image data to populate the first cache;
populating the second cache with a grouping of pixel values of the input image data from the first cache, wherein the grouping of pixel values is selected according to a sliding window that traverses the first cache based on the mapping data; and
interpolating, using the second cache, between input pixel values of the grouping of pixel values to generate one or more output pixel values of the warped image data.