US 12,141,688 B2
Crested barrier device and synaptic element
Milan Pesic, Paoli, PA (US); Shruba Gangopadhyay, San Jose, CA (US); Muthukumar Kaliappan, Fremont, CA (US); and Michael Haverty, Mountain View, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on Jul. 20, 2021, as Appl. No. 17/380,318.
Application 17/380,318 is a continuation in part of application No. 16/857,589, filed on Apr. 24, 2020, granted, now 11,404,636.
Prior Publication US 2021/0350219 A1, Nov. 11, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G06N 3/065 (2023.01); G11C 11/54 (2006.01); G11C 13/00 (2006.01); H10B 63/00 (2023.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC G06N 3/065 (2023.01) [G11C 11/54 (2013.01); G11C 13/0011 (2013.01); H10B 63/84 (2023.02); H10N 70/023 (2023.02); H10N 70/24 (2023.02); H10N 70/8416 (2023.02); H10N 70/8833 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A crested barrier memory device comprising:
a first electrode;
a first self-rectifying layer;
a combined barrier and active layer, wherein:
the first self-rectifying layer is between the first electrode and the active layer;
a conduction band offset between the first self-rectifying layer and the combined barrier and active layer is greater than 1.5 eV; and
a valence band offset between the first self-rectifying layer and the combined barrier and active layer is less than −0.5 eV; and
a second electrode, wherein the active layer is between the first self-rectifying layer and the second electrode.