US 12,141,682 B2
Ultra low-power negative margin timing monitoring method for neural network circuit
Weiwei Shan, Jiangsu (CN); Ziyu Li, Jiangsu (CN); Jun Yang, Jiangsu (CN); and Longxing Shi, Jiangsu (CN)
Assigned to SOUTHEAST UNIVERSITY, Jiangsu (CN)
Filed by SOUTHEAST UNIVERSITY, Jiangsu (CN)
Filed on Feb. 22, 2021, as Appl. No. 17/181,595.
Claims priority of application No. 202011502323.2 (CN), filed on Dec. 18, 2020.
Prior Publication US 2021/0174184 A1, Jun. 10, 2021
Int. Cl. G06N 3/063 (2023.01); G06N 3/04 (2023.01); G06F 119/12 (2020.01)
CPC G06N 3/063 (2013.01) [G06N 3/04 (2013.01); G06F 2119/12 (2020.01)] 7 Claims
OG exemplary drawing
 
1. A negative margin timing monitoring method for a neural network circuit for ultra-low power operation, comprising:
selecting a reversed bit of an accumulator register due to accumulation operation as a timing monitoring unit insertion point according to a bit number of neural network accumulation data and a bit width of the accumulator register in critical paths;
inserting a timing monitoring unit in the critical paths;
replacing all flip-flops from the timing monitoring unit insertion point to a critical path endpoint into latches;
repairing short paths caused by the latches in the critical paths; and
regulating voltage or frequency of the neural network circuit according to an alarm signal generated by the timing monitoring unit.